Computer systems must be provided with sufficient data storage capacity to operate correctly. This data storage capacity is typically provided as Random Access Memory (RAM), and SDRAM is a common form of RAM.
A SDRAM memory chip is divided into banks of memory, and each bank is subdivided into pages. Typically, it is only possible to have one page open in each bank of the chip. When data is to be written to, or read from, a page of the chip which is not open, it is necessary to open that page before the required memory access can be performed. If possible, it is therefore more efficient to perform a series of memory accesses in a single page in succession, before closing that page, opening another page, and then performing a series of memory accesses in that other page in succession.
Accesses to the SDRAM chip are performed by a SDRAM controller, which typically takes the form of a separate, integrated circuit. The SDRAM controller is connected to the SDRAM by means of a memory data bus, and the SDRAM controller must operate as far as possible to maximize efficient use of the bandwidth of that bus.
One known SDRAM controller has multiple inputs, for receiving access requests from different system components. The SDRAM controller then has an arbiter, for prioritizing requests received on the different inputs, and forming a queue of SDRAM commands. The queue of SDRAM commands can then be processed in an order which maximizes efficient use of the bandwidth of the memory data bus, as described above, by grouping in series those access requests which relate to an open page of the SDRAM. Alternatively, the queue of SDRAM commands can then be processed in an order which gives priority to requests received on one or more specific inputs.